Chris Winstead
Electrical and Computer Engineering
Associate Professor
Contact Information
Office Location: EL 304CPhone: 435-797-2871
Email: chris.winstead@usu.edu
Additional Information:
Research Interests
Core Areas: Error correction algorithms, architectures and circuit applications. Probabilistic logic, soft computing and noise-enhanced algorithms. Neuromorphic and Bayesian circuits and systems. Reliability and energy efficiency in signal processing systems. Specialized Interests: Micro-power implementation for communication signal processing. Stochastic and "bit-flipping" algorithms for error correction and signal processing. Probabilistic design for embedded error control in digital circuits. Analog Bayesian circuits for signal-processing in low-power wireless systems. Anomaly detection and attack inference for hardware security. Applications: Implementation of LDPC and Turbo decoders. Bio-implantable and transcutaneous wireless transceivers. Fault-tolerant logic and memories post-CMOS electronics. Circuit-based modeling and synthesis of synthetic biological systems.
Awards
Fulbright Research Scholar, 2014
NSF Career Award, 2010
Outstanding Undergraduate Mentor, 2010
Electrical and Computer Engineering
Publications | Abstracts
- Monzon, E., Tejeda, A., Winstead, C.J, (2012). Detecting Multi- stability in Stochastic Simulations of Gene Networks Using Kernel Density Estimators. International Workshop on Biological Design Automation
- Monzon, E., Tejeda, A., Winstead, C.J, (2012). Using Kernel Density Estimators to Detect Bistable States in Stochastic Simulations of Genetic Circuits. International Workshop on Computational Systems Biology
- Winstead, C.J, Tang, Y., Sundararajan, G., (2012). Techniques and prospects for fault-tolerance in post-CMOS ULSI. International Workshop on Post-Binary ULSI
An asterisk (*) at the end of a publication indicates that it has not been peer-reviewed.
- Kuwahara, H., Madsen, C., Mura, I., Meyers, C., Tejeda, A., Winstead, C.J, (2010). Effecient Stochastic Simulation to Analyze Targeted Properties of Biological Systems: Stochastic Control. InTech
- Winstead, C.J, Schlegel, C., Perez, L., (2004). Low-Density Parity Check Codes: Trellis and Turbo Coding. Wiley-IEEE Press
Publications | Book Chapters
An asterisk (*) at the end of a publication indicates that it has not been peer-reviewed.
Publications | Journal Articles
Academic Journal
- Le, K., Ghaffari, F., Kessal, L., Declercq, D., Boutillon, E., Winstead, C.J, Vasic, B., (2018). A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes. IEEE Trans. on Circuits and Systems I: Regular Papers, 66:1, 403 - 416. doi: 10.1109/TCSI.2018.2849679
- Tithi, T., Gerdes, R., Winstead, C.J, Li, M., Heaslip, K.P, (2018). Analysis of Friendly Jamming for Secure Location Verification of Vehicles. IEEE Transactions on Vehicular Technology, 67:8, 7437 - 7449. doi: 10.1109/TVT.2018.2839560
- Madsen, C., Zhang, Z., Roehner, N., Winstead, C.J, Meyers, C., (2014). Stochastic Model Checking of Genetic Circuits. ACM Journal of Emerging Technologies in Computing - Special Issue on Computational Synthetic Biology and Regular Papers, 11:3, doi: 10.1145/2644817
- Winstead, C.J, Tejeda, A., Monzon, E., Luo, Y., (2014). Error Correction via Restorative Feedback in M-ary Logic Circuits. Journal of Multiple Valued Logic and Soft Computing, 23:3-4
- Winstead, C.J, Boutillon, E., (2014). Decoding LDPC Codes with Locally Maximum-Likelihood Binary Messages. IEEE Communication Letters, 18:12, 2085 - 2088. doi: 10.1109/LCOMM.2014.2366095
- Sundararajan, G., Winstead, C.J, Boutillon, E., (2014). Noisy Gradient Descent Algorithms for Decoding LDPC Codes. IEEE Transactions on Communications, 62:10, 3385-3400. doi: 10.1109/TCOMM.2014.2356458
- Winstead, C.J, Rodrigues, J.N, (2012). Ultra Low Power Error Correction Circuits: Technology Scaling and Sub-VT operation. IEEE Transactions on Circuits and Systems II, 59:12, 913 - 917. doi: 10.1109/TCSII.2012.2231040
- Madsen, C., Myers, C.J, Patterson, T., Roehner, N., Stevens, J., Winstead, C.J, (2012). Design and Test of Genetic Circuits using iBioSim. IEEE Design and Test of Computers, 29:3, 10.1109/MDT.2012.2187875.
- Winstead, C.J, Tehrani, S.S, Mannor, S., Gross, W.J, Howard, S., Gaudet, V.C, (2010). Relaxation Dynamics in Stochastic Iterative Decoders. IEEE Transactions on Signal Processing, 58:11, 5955 - 5961 . doi: 10.1109/TSP.2010.2066269
- Nguyen, N., Meyers, C., Kuwahara, H., Winstead, C.J, Keener, J., (2010). Design and analysis of a robust genetic Mullter C-element. Journal of Theoretical Biology, 264:2, 174 - 187. doi: 10.1016/j.jtbi.2009.10.026
- Winstead, C.J, (2009). C-element multiplexing for fault-tolerant logic circuits. IET Electronics Letters, 45:19, 969 – 970 . doi: 10.1049/el.2009.1073
- Winstead, C.J, Howard, S., (2009). A Probabilistic LDPC-Coded Fault Compensation Technique for Reliable Nanoscale Computing. IEEE Transactions on Circuits and Systems II - Express Briefs, 56:6, 484 - 488 . doi: 10.1109/TCSII.2009.2020946
- Haley, D., Winstead, C.J, Gaudet, V., Schlegel, C., (2009). A dual-function mixed-signal circuit for LDPC encoding/decoding. Integration: The VLSI Journal, 42:3, 332 - 339. doi: 10.1016/j.vlsi.2008.09.006
- Winstead, C.J, El Hamoui, M., (2009). Reducing clock jitter by using Muller-C elements. IET Electronics Letters, 45:3, 150 - 151. doi: 10.1049/el:20093196
- Kashyap, M., Winstead, C.J, (2008). Decoding LDPC Convolutional Codes on Markov Channels. EURASIP Journal on Wireless Communications and Networking, doi: 10.1155/2008/729180
- Yiu, M., Winstead, C.J, Gaudet, V., Schlegel, C., (2007). Design for Testability of CMOS Analog Sum-Product Error Control Decoders. IEEE Transactions on Circuits and Systems II: Express Briefs, 54:8, 675 - 680. doi: 10.1109/TCSII.2007.898472
- Winstead, C.J, Nguyen, N., Gaudet, V., Schlegel, C., (2006). Low-voltage CMOS circuits for analog iterative decoders. IEEE Transactions on Circuits and Systems I, 53:4, 829 - 841 . doi: 10.1109/TCSI.2005.859773
- Winstead, C.J, Dai, J., Yu, S., Myers, C., Harrison, R.R, Schlegel, C., (2004). CMOS analog MAP decoder for (8,4) Hamming code. IEEE Journal of Solid-State Circuits, 39:1, 121 - 131. doi: 10.1109/JSSC.2003.820845
An asterisk (*) at the end of a publication indicates that it has not been peer-reviewed.
Publications | MultiMedia
Video
An asterisk (*) at the end of a publication indicates that it has not been peer-reviewed.
Publications | Other
An asterisk (*) at the end of a publication indicates that it has not been peer-reviewed.
Teaching
Creative Works | Performances
- Turtle Dove, Music Performance - Major Participant, Opera/Musical,