ECE 5530 Schedule (Fall 2010)

Lecture schedule

Date	Lectures	Readings	Posted	Due
8/30/10	L1: HDL overview	Chapter 2: 2.9
9/1/10	L2: Introduction to Verilog	Chapter 2: 2.10	HW1
9/3/10	L3: Verilog Contd.	Chapter 2: 2.10
9/6/10	Labor day
9/8/10	L4: Verilog signals, numbers	Appendix A: A.1-A.11.1
9/10/10	L5: Adders	Chapter 5: 5.2		HW1
9/13/10	L6: Adders Contd.	Chapter 5: 5.2
9/15/10	L7: Adders, Subtractors	Chapter 5: 5.2.2-5.3.5	HW2, Lab 1
9/17/10	L8: Carry Lookahead Adder	Chapter 5: 5.4		Lab 1
9/20/10	L9: CLA, Adders in Verilog	Chapter 5: 5.4-5.5.3
9/22/10	L10: Adders, Multiplication	Chapter 5: 5.5.4-5.6.1	Lab 2
9/24/10	L11: Multiplication	Chapter 5: 5.6		HW2, Lab 2
9/27/10	L12: Other numbers	Chapter 5: 5.7
9/29/10	L13: BCD, Simulation	-	HW3
10/1/10	L14: Simulation, Testbenches	-
10/4/10	L15: Procedural Assignments	Chapter 7: 7.12.3
10/6/10	L16: Procedural assignments	Chapter 7: 7.12.4
10/8/10	Midterm Review			HW3
10/11/10	Midterm Exam
10/13/10	L17: Multiplexers	Chapter 6: 6.1
10/14/10	Midterm solutions
10/15/10	Fall break
10/18/10	L18: Shannon, Decoders	Chapter 6: 6.1-6.2	Lab 3
10/20/10	L19: Decoders, Encoders	Chapter 6: 6.2-6.3
10/22/10	L20: Code converters, Verilog	Chapter 6: 6.4-6.6
10/25/10	L21:Verilog task and functions	Chapter 6: 6.6.3-6.6.7
10/27/10	L22: Latches	Chapter 7: 7.1-7.3	HW4	Lab 3
10/29/10	L23: Flip-flops	Chapter 7: 7.4-7.7
11/1/10	L24: Counters	Chapter 7: 7.8-7.9
11/3/10	L25: Counters	Chapter 7: 7.9-7.11	Project
11/5/10	L26: Verilog for storage elements	Chapter 7: 7.12-7.13		HW4, Lab 4
11/8/10	L27: Bus design	Chapter 7: 7.14.1
11/10/10	L28: Processor design	Chapter 7: 7.14.2	HW5
11/12/10	L29: Synthesis Issues	-
11/15/10	L30: FSM	Chapter 8: 8.1
11/17/10	L31: FSM	Chapter 8: 8.1-8.4
11/19/10	No class
11/22/10	L32: FSM design	Chapter 8: 8.5		HW5
11/24/10	Thanksgiving break
11/26/10	Thanksgiving break
11/29/10	L33: State minimization	Chapter 8: 8.6	HW6
12/1/10	No class
12/3/10	L34: Design Examples	Chapter 10: 10.2
12/6/10	L35: Design Examples	Chapter 10: 10.2		HW6
12/8/10	No class
12/10/10	Project demos			Project Report
12/15/2010	Final Exam

Lab Schedule

Date	Labs (held in Design Automation Lab)
9/2/10	No lab
9/9/10	No lab
9/16/10	Lab 1: Modelsim tutorial
9/23/10	Lab 2: Adder design
9/30/10	No Lab
10/7/10	No Lab
10/14/10	No Lab: Friday Schedule
10/21/10	Lab 3: Muxes and Matrix multiplication
10/28/10	No lab
11/4/10	Lab 4: Synthesis using Design Vision
11/11/10	Work on project
11/18/10	Lab 4a, Work on project
11/25/10	Thanksgiving break
12/2/10	Work on project
12/9/10	Work on project