ECE 5470/6470 Schedule (Spring 2010)

CVD: CMOS VLSI Design; HPMC: Design of High-Performance Microprocessor Circuits

Date Lecture Reading Due
01/12 CMOS Transistor Theory CVD: 2.1-2.2  
01/14 MOS Capacitance, DC Transfer Characteristic CVD: 2.3,2.5  
01/19 DC Transfer, Nonideal Effects CVD: 2.5, 2.4  
01/21 Nonideal Effects, ASIC standard cell tool flow CVD: 2.4  
01/26 Transistor Scaling   Homework 1
01/28 Transistor Scaling CVD: 4.9; HPMC: 1.6  
02/02 Interconnect Scaling, ITRS CVD: 4.9.2-4.9.4 Lab 1
02/04 Scaling Issues HPMC: 2  
02/09 Timing estimation and optimization CVD: 4.1-4.2  
02/11 Elmore delay estimation CVD: 4.2 Homework 2, Lab 2 (Feb 12)
02/16 No class (Monday Schedule)    
02/18 Logical Effort CVD 4.2.2-4.3.1  
02/23 Delay in Multistage Logic Networks CVD 4.3.2  
02/25 Best stages, Timing Verification start CVD: 4.3.3-4.3.6 Lab 2b
03/02 Timing Verification HPMC: 23.1-23.2  
02/04 Timing Analysis, Clocking HPMC: 23.3; CVD: 7.1-7.2 Homework 3
03/09 Midterm Review    
03/11 Midterm Exam    
03/16 Spring break    
03/18 Spring break    
03/23 No class    
03/25 Project meetings (No class)   Lab 3 (03/26)
03/30 Project meetings (No class)    
04/01 Process Variation HPMC: 6.1 Project Proposal
04/06 Process Variation HPMC: 6.2-6.3  
04/08 Circuit families CVD: 6.1-6.2.1  
04/13 Circuit families CVD: 6.2.1-6.2.2 Midterm Progress Report
04/15 Circuit families CVD: 6.2.2,6.2.4  
04/20 Circuit families CVD: 6.2.4 Lab 4
04/22 No class   Homework 4
04/27 Project presentation    
04/29 No class    
04/30 -   Final report
  05/06 Final Examination